AT89C51ID2-RLRIM【PDF 141/157 页】IC MCU FLASH 8051 64K 5V 44-VQFP

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AT89C51ID2

4289C–8051–11/05

When the slave address and the direction bit have been transmitted and an acknowl-

edgement bit has been received, the serial interrupt flag is set again and a number of

status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and

also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate

action to be taken for each of these status code is detailed in Table . This scheme is

repeated until a STOP condition is transmitted.

SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to

Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may

switch to the master transmitter mode by loading SSDAT with SLA+W.

Slave Receiver Mode

In the slave receiver mode, a number of data bytes are received from a master transmit-

ter (Figure 34). To initiate the slave receiver mode, SSADR and SSCON must be loaded

as follows:

The upper 7 bits are the address to which the TWI module will respond when addressed

by a master. If the LSB (GC) is set the TWI module will respond to the general call

address (00h); otherwise it ignores the general call address.

CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the

TWI. The AA bit must be set to enable the own slave address or the general call address

acknowledgement. STA, STO and SI must be cleared.

When SSADR and SSCON have been initialised, the TWI module waits until it is

addressed by its own slave address followed by the data direction bit which must be at

logic 0 (W) for the TWI to operate in the slave receiver mode. After its own slave

address and the W bit have been received, the serial interrupt flag is set and a valid sta-

tus code can be read from SSCS. This status code is used to vector to an interrupt

service routine.The appropriate action to be taken for each of these status code is

detailed in Table . The slave receiver mode may also be entered if arbitration is lost

while TWI is in the master mode (states 68h and 78h).

If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1)

to SDA after the next received data byte. While AA is reset, the TWI module does not

respond to its own slave address. However, the 2-wire bus is still monitored and

address recognition may be resume at any time by setting AA. This means that the AA

bit may be used to temporarily isolate the module from the 2-wire bus.

Slave Transmitter Mode

In the slave transmitter mode, a number of data bytes are transmitted to a master

receiver (Figure 35). Data transfer is initialized as in the slave receiver mode. When

SSADR and SSCON have been initialized, the TWI module waits until it is addressed by

Table 63. SSADR: Slave Receiver Mode Initialization

own slave address

Table 64. SSCON: Slave Receiver Mode Initialization

CR2

SSIE

STA

STO

CR1

CR0

bit rate

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